View LU3X32FT_3222640.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary data sheet july 2000 LU3X32FT two-port 3 v 10/100 ethernet transceiver tx/fx note: for sustaining support only, not for new designs. overview the LU3X32FT is a fully integrated two-port 10 mbits/s/100 mbits/s physical layer device with transceiver. this part was designed for 10 mbits/s/ 100 mbits/s applications where board space, cost, and power are at a premium and stringent functional interoperability is a necessity. operating at 3.3 v, the LU3X32FT is a powerful device for the forward migration of legacy 10 mbits/s products and noncompliant 100 mbits/s devices. the LU3X32FT was designed from the beginning to conform fully with all pertinent specifications, from the iso/iec 11801 and eia/tia 568 cabling guidelines to ansi x3.263 tp-pmd to ieee * 802.3 ethernet specifications. features n single-chip integrated two-port physical layer and transceiver for 10base-t and/or 100base-t func- tions n ieee 802.3 compatible 10base-t and 100base-t physical layer interface and ansi x3.263 tp-pmd compatible transceiver n pecl interface for external fx transceiver n built-in analog 10 mbits/s receive filter, removing the need for external filters n built-in 10 mbits/s transmit filter n 10 mbits/s pll exceeding tolerances for both pre- amble and data jitter n 100 mbits/s pll, combined with the digital adap- tive equalizer, robustly handles variations in rise- fall time, excessive attenuation due to channel loss, duty-cycle distortion, crosstalk, and baseline wander n transmit rise-fall time manipulated to provide lower emissions, amplitude fully compatible for proper interoperability n programmable scrambler seed for better fcc compliancy n selectable cim, class ii support, and powerful mii drivers for repeater applications n ieee 802.3u clause 28 compliant autonegotiation for full 10 mbits/s and 100 mbits/s control n fully configurable via pins and management accesses n phy mib support n symbol mode option n low-power C300 ma max n low autonegotiation power C30 ma/port n very low powerdown mode <5 ma/port n 128-pin tqfp package * ieee is a registered trademark of the institute of electrical and electronics engineers, inc.
table of contents contents page LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 2 lucent technologies inc. overview....................................................................................................................... ............................................ 1 features ....................................................................................................................... ............................................ 1 description.................................................................................................................... ............................................ 4 pin information ................................................................................................................ ......................................... 5 pin descriptions............................................................................................................... ......................................... 6 functional description ......................................................................................................... ................................... 12 media independent interface (mii) .............................................................................................. ........................ 12 100base-x module............................................................................................................... ............................... 15 10base-t module ................................................................................................................ ................................ 21 clock synthesizer.............................................................................................................. .................................. 23 autonegotiation ................................................................................................................ ................................... 24 reset operation ................................................................................................................ .................................. 25 register descriptions .......................................................................................................... ................................... 27 absolute maximum ratings (ta = 25 c)............................................................................................................... 40 electrical characteristics ..................................................................................................... ................................... 41 clock timing................................................................................................................... ........................................ 42 outline diagram................................................................................................................ ...................................... 53 128-pin tqfp ................................................................................................................... .................................. 53 ta bl es page table 1. twisted-pair magnetic interface ...................................................................................... ........................... 6 table 2. fiber-optic transceiver interface .................................................................................... ........................... 6 table 3. twisted-pair transceiver control ..................................................................................... ........................... 6 table 4. mii interface ........................................................................................................ ....................................... 6 table 5. phy address configuration ............................................................................................ ........................... 7 table 4. mii interface (continued) ............................................................................................ ................................ 7 table 6. 100 base-x pcs configuration......................................................................................... ......................... 8 table 7. autonegotiation configuration ........................................................................................ ............................ 8 table 8. special mode configurations .......................................................................................... ........................... 9 table 9. led and status outputs ............................................................................................... ........................... 10 table 10. clock and chip reset ................................................................................................ ............................ 11 table 11. power and ground .................................................................................................... ............................. 11 table 12. symbol code scrambler ............................................................................................... ......................... 17 table 13. initial value of autonegotiation registers.......................................................................... ..................... 26 table 14. mii management registers legends .................................................................................... ................. 27 table 15. control register (per port) [register 0h] ........................................................................... .................... 28 table 16. status register bit definitions (per port) [register 1h]............................................................ .............. 30 table 17. phy identifier (per port) [register 2h] ............................................................................. ...................... 31 table 18. phy identifier (per port) [register 3h] ............................................................................. ...................... 31 table 19. advertisement (per port) [register 4h] .............................................................................. .................... 32 table 20. autonegotiation link partner ability (per port) [register 5h]....................................................... ........... 32 table 21. autonegotiation expansion register (per port) [register 6h] ......................................................... ....... 33 table 22. ............................................................................................... isolate counter (per port) [register 12h]33 table 23. false carrier counter (per port) [register 13h] ..................................................................... ................ 33 table 24. receive error counter (per port) [register 15h]..................................................................... ............... 34 table 25. phy control/status register (per port) [register 17h]............................................................... ........... 34 table 26. config 100 register (per port) [register 18h]....................................................................... ................. 36 table 27. ....................................................................................phy address register (per port) [register 19h]37 table 28. config 10 register (per port) [register 1ah] ........................................................................ ................. 37 table 29. status 100 register (per port) [register 1bh] ....................................................................... ................ 38
lucent technologies inc. 3 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx table of contents (continued) tables page table 30. status 10 register (per port) [register 1ch] ....................................................................... ..................38 table 31. interrupt mask register (per port) [register 1dh] ................................................................... ...............38 table 32. interrupt status register (per port) [register 1eh]................................................................. ................39 table 33 . absolute maximum ratings ........................................................................................... ........................40 table 34 . operating conditions ............................................................................................... ..............................40 table 35. dc characteristics .................................................................................................. .................................41 table 36. system clock [xin].................................................................................................. ................................42 table 37. transmit clock (input and output) ................................................................................... .......................43 table 38. management clock .................................................................................................... .............................44 table 39. mii receive timing .................................................................................................. ...............................45 table 40. mii transmit timing................................................................................................. ................................46 table 41. transmit timing..................................................................................................... ..................................47 table 42. receive timing ...................................................................................................... .................................48 table 43. reset and configuration timing ...................................................................................... .......................49 table 44. pmd characteristics ................................................................................................. ..............................50 figures page figure 1. LU3X32FT block diagram (per port) ................................................................................... .....................4 figure 2. pin diagram ......................................................................................................... .....................................5 figure 3. 100base-x data path (per port) ...................................................................................... .......................15 figure 4. 10base-t module data path (per port) ................................................................................ ...................21 figure 5. hardware reset configurations ....................................................................................... ....................25 figure 6. system clock [xin] .................................................................................................. ...............................42 figure 7. transmit clock (input and output) ................................................................................... .......................43 figure 8. management clock .................................................................................................... .............................44 figure 9. mii receive timing .................................................................................................. ...............................45 figure 10. mii transmit timing................................................................................................ ...............................46 figure 11. transmit timing.................................................................................................... .................................47 figure 12. receive timing ..................................................................................................... ................................48 figure 13. reset and configuration timing ..................................................................................... ......................49 figure 14. pmd characteristics ................................................................................................ .............................50 figure 15. connection diagrams (frequency references) ......................................................................... ...........51 figure 16. connection diagrams (10/100btx operation) .......................................................................... ...........52
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 4 lucent technologies inc. description 5-6779(f).r1 figure 1. LU3X32FT block diagram (per port) mii interface logic led s led s management interface register/ config/ control 10/100-rx pcs 10/100-tx pcs 10/100-tx drivers autoneg rx10 squelch clock synthesis and recovery adaptive equalizer baseline wander correction mdio mdc txd txen txer txclk miiena rxd rxdv rxer rxclk col/fcrs crs mdioint fotx tptx forx fosd tprx
lucent technologies inc. 5 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx pin information 5-8343(f).r1 figure 2. pin diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 fosd+/srl10[0] ref10[1] ref100[1] rxvdd2[0] rxgnd2[0] tprxC[0] tprx+[0] rxgnd1[0] rxvdd1[0] fovdd[0] csvdd[0] csgnd[0] fotxC[0] fotx+[0] txvdd2[0] tptxC[0] tptx+[0] txgnd1[0] txvdd1[0] txvdd1[1] txgnd1[1] tptx+[1] tptxC[1] txvdd2[1] fotx+[1] fotxC[1] csgnd[1] csvdd[1] fovdd[1] rxvdd1[1] rxgnd1[1] tprx+[1] tprxC[1] rxgnd2[1] rxvdd2[1] ref100[0] ref10[0] fosd+/srl10[1] 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 forxC[1] forx+[1] 100fden/cimen[1] gnd9[1] autonen[1] eqgnd1[1] eqvdd1[1] miiena[1] rstz[1] xtlvdd[0] fosel[1] mdc[0] ledlnk/bpalign[0] ledfd/10hden/fefi_en[0] ledcol/bp4b5b[0] ledtx/actled/bpscr[0] ledrx/ndrptr[0] col/phy[4]/fcrs[0] vdd6[0] phy[1][1] vdd5[1] mdio[0] crs/phy[3][0] txclk[0] txd0[0] txd1[0] txd2[0] txd3[0] txer[0] txen[0] gnd8[0] vdd8[0] gnd2[0] vdd2[0] rxclk[0] rxd0[0] rxd1[0] rxd2[0] rxd3[0] rxer[0] rxdv[0] 10fden/ledsp[0] mdiointz/phy[2][0] mdiointz/phy[2][1] 10fden/ledsp[1] rxdv[1] rxer[1] rxd3[1] rxd2[1] rxd1[1] rxd0[1] rxclk[1] vdd2[1] gnd2[1] vdd8[1] gnd8[1] txen[1] txer[1] txd3[1] txd2[1] txd1[1] txd0[1] 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 txclk[1] crs/phy[3][1] mdio[1] vdd5[0] phy[1][0] vdd6[1] col/phy[4]/fcrs[1] ledtx/actled/bpscr[1] ledcol/bp4b5b[1] led/10hden/fefi_en[1][1] ledlnk/bpalign[1] mdc[1] fosel[0] xtlvdd[1] rstz[0] miiena[0] eqvdd1[0] eqgnd1[0] autonen[0] xin[1] gnd9[0] 100fden/cimen[0] forx+[0] forxC[0] fosdC/rptr10clk[0] 104 ledrx/ndrptr[1] fosdC/rptr10clk[1] xin[0]
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 6 lucent technologies inc. pin descriptions table 1. twisted-pair magnetic interface table 2. fiber-optic transceiver interface note: many of these signals are dual-function pins. during reset, these pins may be pulled up or down (as shown in figure 5) to configure various options. the secondary function is shown in smaller print and described in table 8. table 3. twisted-pair transceiver control table 4. mii interface pin no. pin name i/o pin descri p tion 22, 17 23, 16 tptx+[1:0] tptxC[1:0] o twisted-pair transmit driver pairs . these pins are used to send 100base-t mlt-3 signals or 10base-t manchester signals across utp cable. 32, 7 33, 6 tprx+[1:0] tprxC[1:0] i twisted-pair receive pair . these pins receive 100base-t mlt-3 data or 10base-t manchester data from the utp cable. pin no. pin name i/o pin descri p tion 25, 14 26, 13 fotx+[1:0] fotxC[1:0] o fiber-optic transmit driver pair . these pins are used to transmit differential pecl level nrzi data to a fiber- optic transceiver. 41, 126 40, 127 forx+[1:0] forxC[1:0] i fiber-optic receive pair . these pins are used to receive differential pecl level nrzi data from a fiber- optic transceiver. 38, 1 39, 128 fosd+ /srl10 [1:0] fosdC/ rptr10clk [1:0] i fiber-optic signal detect differential input pair . while operating in fiber mode, these pins are used to detect whether or not the fiber-optic receive pairs are receiving valid signal levels. see table 8 for srl10 and rptr10clk desscriptions. if fiber and serial 10 modes are not being used, tie all these pins low. pin no. pin name i/o pin descri p tion 36, 3 ref100[1:0] i reference pin for 100 mbits/s twisted-pair driver . the value of the connected resistor is 301 w . 37, 2 ref10[1:0] i reference pin for 10 mbits/s twisted-pair driver . the value of the connected resistor is 4.64 k w . pin no. pin name i/o pin descri p tion 86, 81 rxdv[1:0] o receive data valid . 87, 80 rxer[1:0] o receive error . 88, 79 rxd3[1:0] o receive data[3] . 89, 78 rxd2[1:0] o receive data[2] . 90, 77 rxd1[1:0] o receive data[1] . 91, 76 rxd0[1:0] o receive data[0] . 92, 75 rxclk[1:0] o receive clock . 97, 70 txen[1:0] i transmit enable . 98, 69 txer[1:0] i transmit error . 99, 68 txd3[1:0] i transmit data[3] .
lucent technologies inc. 7 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx note: many of these signals are dual-function pins. during reset, these pins may be pulled up or down (as shown in figure 5) to configure various options. the secondary function is shown in smaller print and described in table 5. table 5. phy address configuration 100, 67 txd2[1:0] i transmit data[2] . 101, 66 txd1[1:0] i transmit data[1] . 102, 65 txd0[1:0] i transmit data[0] . 103, 64 txclk[1:0] o transmit clock . this pin outputs during node mode only. for 100 mbits/s repeater mode, all transmit related mii signals should be synchronized to 25 mhz clock on xin pin. see table 8 for 10 mbits/s repeater mode clock- ing. 104, 63 crs /phy[3] [1:0] i/o carrier sense/phy address [3] . this output pin indi- cates the carrier sense condition. it is only active on receive while in repeater mode. see table 5 for phy[3] description. 109, 58 col/fcrs /phy[4] [1:0] i/o collision/false carrier sense . this output pin indi- cates collision condition in node operation and indicates false carrier sense condition in repeater mode. this out- put is squelch jabber in 10 mbits/s mode. see table 5 for phy[4] description. 105, 62 mdio[1:0] i/o management data i/o . 115, 52 mdc[1:0] i management data clock . 119, 48 miiena[1:0] i mii enable . a logic 0 on this pin tri-states all rx inter- face signals of mii. this pin is intended to be used by the repeater controller to selectively enable one of the phys in the system. for node applications, this pin is ignored. 84, 83 mdiointz /phy[2] [1:0] i/o mdio interrupt (active-low) . the mdio interrupt pin outputs a logic 0 pulse of 40 ns, synchronous to xin, whenever an unmasked interrupt condition is detected. refer to management registers 1dh and 1eh for inter- rupt conditions. see table 5 for phy[2] description. pin no. pin name i/o pin descri p tion 107, 60 84, 83 104, 63 109, 58 phy[0] phy[1][1:0] phy[2] /mdiointz [1:0] phy[3] /crs [1:0] phy[4] /col/fcrs [1:0] i i/o i/o i/o phy address [4:1] . these 8 pins are detected during powerup or reset to initialize the phy address used for mii management register interface. phy address 00h forces the phy into mii isolate mode. phy address pins [4:2] have an internal 40 k w pull-down. phy address [0] is forced to 0 for port 0, and 1 for port 1. see table 4 for mdiointz, crs, col, and fcrs descriptions. pin no. pin name i/o pin descri p tion pin descriptions (continued) table 4. mii interface (continued)
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 8 lucent technologies inc. table 6. 100 base-x pcs configuration note: many of these signals are dual-function pins. during reset, these pins may be pulled up or down (as shown in figure 5) to configure various options. the secondary function is shown in smaller print and described in table 9. table 7. autonegotiation configuration pin no. pin name i/o pin descri p tion 111, 56 bpscr /ledtx/ actled [1:0] i/o bypass scrambler mode (ports 1, 0) . a high value on this pin during powerup or reset will bypass the scram- ble/descramble operations in the 100base-x data path. this pin has an internal 40 k w pull-down. in fiber mode, this pin should be pulled high. see table 9 for ledtx and actled description. 114, 53 bpalign /ledlnk [1:0] i/o bypass alignment mode (ports 1, 0) . a high value on this pin during powerup or reset will bypass the align- ment feature of the phy. this bypass mode provides a symbol interface. this pin has an internal 40 k w pull- down. see table 9 for ledlnk description. 112, 55 bp4b5b/ ledcol [1:0] i/o bypass 4b5b mode. a high value on this pin during powerup or reset will bypass the 4b/5b encoder of the phy. this pin has an internal 40 k w pull-down. see table 9 for ledcol description. pin no. pin name i/o pin descri p tion 122, 45 autonen[1:0] i autonegotiation enable (ports 1, 0) . a high value on these pins during powerup or reset will enable autone- gotiation, a low value will disable it. 125, 42 100fden /cimen [1:0] i 100 full-duplex enable (ports 1, 0) . logic level of this pin is detected at powerup or reset to determine whether 100 mbits/s full-duplex mode is available. the 100 mbits/s full-duplex mode is available only if ndprtr pin is low during reset indicating node operation. when autonegotiation is enabled, this input sets the ability register bit in advertisement register 4. when autonego- tiation is not enabled, this input will select the mode of operation. see table 8 for cimen description. 85, 82 10fden /ledsp [1:0] i/o 10 full-duplex enable (ports 1, 0) . logic level of this pin is detected at powerup or reset to determine whether 10 mbits/s full-duplex mode is available. the 10 mbits/s full-duplex mode is available only if ndprtr pin is low during reset indicating node operation. when autonegotiation is enabled, this input sets the ability register bit in advertisement register 4. when autonego- tiation is not enabled, this input will select the mode of operation. this pin has an internal 40 k w pull-up resistor. see table 9 for ledsp description. pin descriptions (continued)
lucent technologies inc. 9 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx note: many of these signals are dual-function pins. during reset, these pins may be pulled up or down (as shown in figure 5) to configure various options. the secondary function is shown in smaller print and described in table 8. table 8. special mode configurations 113, 54 10hden/ ledfd/fefi- en [1:0] i/o 10 half-duplex enable . the logic level of this pin is detected at powerup or reset to determine whether 10mbits/s half-duplex mode is available. when autone- gotiation is enabled, this input sets the ability register bit in advertisement register 4. when autonegotiation is not enabled, this input will select the mode of operation. this pin has an internal 40 k w pull-up resistor. see table 8 for fefi_en and table 9 for ledfd descriptions. pin no. pin name i/o pin descri p tion 110, 57 ndrptr /ledrx [1:0] i/o node-repeater select (ports 1, 0) . these pins are detected during powerup or reset to determine the mode of operation. if this pin is at logic high level, then the phy will go into repeater mode; otherwise, if logic low it will operate in node mode. these pins have an internal 40 k w pull-down. see table 9 for ledrx description. 125, 42 cimen /100fden [1:0] i carrier integrity monitor enable (ports 1, 0) . the cim function is only used for repeater operation. if both ndrptr pin and cimen pin are at logic high level dur- ing powerup or reset, then the cim function is enabled. see table 7 for 100fden description. 116, 51 fosel[1:0] i fiber-optic mode select . this pin is tested during pow- erup or reset only. if this pin is detected to be at logic high level, then the phy goes into fiber-optic mode. 38, 1 srl10 /fosd+ [1:0] i serial mode select . at powerup or reset, if fosel pin is pulled low and srl10 is pulled high, then the mii interface will be operated in serial mode for 10 mbits/s operation. fiber-optic mode and 10 mbits/s serial mode cannot be set at the same time. note that the serial mode is only supported for 10 mbits/s repeater opera- tion. see table 2 for fosd+ description. 128, 39 rptr10clk/ fosdC [1:0] i/o 10 mbits/s repeater clock . for 10 mbits/s repeater mode, an external 10 mhz clock should be connected to this pin for clocking of the transmit data. see table 2 for fosdC description. 113, 54 fefi_en/ 10hden/ ledfd [1:0] i/o far-end fault indicator enable . at powerup or reset, if fosel pin is set high, logic level of this pin is latched into bit 11 of register 18h. this pin has an internal 40 k w pull-up resistor. see table 7 for 10hden and table 9 for ledfd description. pin no. pin name i/o pin descri p tion pin descriptions (continued) table 7. autonegotiation configuration (continued )
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 10 lucent technologies inc. table 9. led and status outputs pin no. pin name i/o pin descri p tion 110, 57 ledrx /ndrptr [1:0] i/o receive led (ports 1, 0) . this output will drive a 10 ma led if the phy is receiving data from the utp cable. place a 10 k w resistor across the led pins if setting to nondefault mode, i.e., repeater mode. see table 8 for ndrptr description. 111, 56 ledtx/actled / bpscr [1:0] i/o transmit led or activity led (ports 1, 0) . when bit 7 of register 17h is 0, this output will drive a 10 ma led if the phy is transmitting data; if the control bit is set, then the led will be driven whenever there is a receive or transmit over the cable. place a 10 k w resistor across the led pins if setting to nondefault mode, i.e., bypass scrambler mode. see table 6 for bpscr description. 114, 53 ledlnk /bpalign [1:0] i/o link led (ports 1, 0) . this output will drive a 10 ma led for as long as a valid link exists across the cable. place a 10 k w resistor across the led pins if setting to nondefault mode, i.e., bypass align mode. see table 6 for bpalign description. 85, 82 ledsp /10fden [1:0] i/o speed status (ports 1, 0) . this output can be used to drive a 10 ma led for as long as the phy is in 100 mbits/s mode. place a 10 k w resistor across the led pins if setting to nondefault mode, i.e., 10fd dis- able mode. see table 7 for 10fden description. 113, 54 ledfd/ 10hden/ fefi_en [1:0] i/o full-duplex status . this output will drive a 10 ma led when the LU3X32FT is in full-duplex mode. place a 10 k w resistor across the led pins if setting to nondefault mode, i.e., 10hd disable mode, as shown in figure 5. see table 7 for 10hden and table 8 for fefi_en description. 112, 55 ledcol/ bp4b5b [1:0] i/o collision led . this output will drive a 10 ma led whenever the phy senses a collision has occurred. place a 10 k w resistor across the led pins if setting to nondefault mode, i.e., bypass 4b/5b mode. see table 6 for bp4b5b description.
lucent technologies inc. 11 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx pin descriptions (continued) table 10. clock and chip reset table 11. power and ground pin no. pin name i/o pin descri p tion 123, 44 xin[1:0] i 25 mhz clock input (ports 1, 0) . 118, 49 rstz[1:0] i reset (ports 1, 0) (active-low) . plane v cc pin associated ground pin name pin no. name pin no. rx analog rxv dd 1[1:0] rxv dd 2[1:0] 30, 9 35, 4 rxgnd1[1:0] rxgnd2[1:0] 31, 8 34, 5 tx analog txv dd 1[1:0] txv dd 2[1:0] 20, 19 24, 15 txgnd1[1:0] 21, 18 cs csv dd [1:0] fov dd 10[1:0] 28, 11 29, 10 csgnd[1:0] 27, 12 digital v dd 2[1:0] v dd 5[1:0] v dd 6[1:0] v dd 8[1:0] eqv dd 1[1:0] 93, 74 106, 61 108, 59 95, 72 120, 47 gnd2[1:0] gnd8[1:0] gnd9[1:0] eqgnd1[1:0] 94, 73 96, 71 124, 43 121, 46 clock xtlv dd [1:0] 117, 50
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 12 lucent technologies inc. functional description the LU3X32FT integrates a 100base-x physical sublayer (phy), a 100base-tx physical medium dependent (pmd) transceiver and a complete 10base-t module into a single chip for both 10 mbits/s and 100 mbits/s ethernet operation for two-ports. it also supports 100base-fx operation through external fiber-optic transceivers. this device provides two ieee 802.3u compliant media independent interfaces (mii) to communicate between the phys- ical signaling and the medium access control (mac) layers for both 100base-x and 10base-t operations. the device is capable of operating in either full-duplex mode or half-duplex mode in either 10 mbits/s or 100 mbits/s operation independently per port. operational modes can be selected by hardware configuration pins or software settings of management registers, or they can be determined by the on-chip autonegotiation logic. the 10base-t section of each port consists of the 10 mbits/s transceiver modules with filters and manchester endec modules. the 100base-x section of the each port implements the following functional blocks: n 100base-x physical coding sublayer (pcs) n 100base-x physical medium attachment (pma) n twisted-pair transceiver (pmd) the 100base-x and 10base-t sections of each port share the following functional blocks: n clock synthesizer module (csm) n mii registers n ieee 802.3u autonegotiation each of these functional blocks is described below. media independent interface (mii) the LU3X32FT implements an ieee 802.3u clause 22 compliant mii interface as described below. interface signals transmit data interface . each mii transmit data interface comprises seven signals: txd[3:0] are the nibble size data path, txen signals the presence of data on txd, txer indicates substitution of data with the halt symbol, and txclk carries the transmit clock that synchronizes all the transmit signals. in node mode, txclk is supplied by the on-chip clock synthesizer; in 100 mbits/s repeater mode, transmit signals are synchronized to the clock on xin pin; in 10 mbits/s repeater mode operation, an external clock must be connected to the rptr10clk pin to synchronize the data transfer. receive data interface . each mii receive data interface also comprises seven signals: rxd[3:0] are the nibble size data path, rxdv signals the presence of data on rxd, rxer indicates the validity of data, and rxclk carries the receive clock. depending upon the operation mode, rxclk signal is generated by the clock recovery module of either the 100base-x or 10base-t receiver. status interface . two status signals, col and crs, are generated in the LU3X32FT to indicate collision status and carrier sense status to the mac for each port. col is asserted asynchronously whenever that port is transmit- ting and receiving at the same time in a half-duplex operation mode. in full-duplex mode, col is inactive. for repeater mode operation, the col signal line indicates false carrier sense condition. crs is asserted asynchro- nously whenever there is activity on either the transmitter or the receiver. in repeater or full-duplex mode, crs is asserted only when there is activity on the receiver.
lucent technologies inc. 13 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx functional description (continued) operation modes each port of the LU3X32FT supports three operation modes and an isolate mode as described below. 100 mbits/s mode . for 100 mbits/s operation, the mii operates in nibble mode with a clock rate of 25 mhz. in nor- mal operation, the mii data at rxd[3:0] and txd[3:0] are 4-bit wide. in bypass mode (either byp_4b5b or byp_align option selected), the mii data takes the form of 5-bit code-groups. the least significant 4 bits appear on txd[3:0] and rxd[3:0] as usual, and the most significant bits (txd[4] and rxd[4]) appear on the txer and rxer pins, respectively. 10 mbits/s nibble mode . for 10 mbits/s nibble mode operation, the txclk and rxclk operate at 2.5 mhz. the data paths are 4 bits wide using txd[3:0] and rxd[3:0] signal lines. this mode is not supported for repeaters. 10 mbits/s serial mode . the LU3X32FT implements a serial mode for 10base-t repeater applications. this mode is selected by strapping the ndrptr pin (57, 110) and srl10 pin (pins 1, 38) to logic high level and hold fosel pin (pins 116, 51) at logic low level during powerup or reset. when operating in this mode, the LU3X32FT accepts nrz serial data on the txd[0] input and provides nrz serial data output on rxd[0] with a clock rate of 10 mhz. the unused mii signals txd[3:1], rxd[3:1], and rxdv are ignored during serial mode. the pcs control signals crs and col continue to function normally. mii isolate mode . the LU3X32FT implements an mii isolate mode that is controlled by bit 10 of the control register (register address 0h). the LU3X32FT will set this bit to one if the phy address is set to 00000 upon powerup/hard- ware reset. otherwise, the LU3X32FT will initialize this bit to 0. setting the bit to a 1 will also put the phy in mii iso- late mode. note that port 1 cannot powerup/reset into isolate mode, since its phy[0] is forced to 1; however, it can be programmed into isolate mode by setting bit 10 of the control register (register 0h). the isolate mode can also be activated by setting the phy address (bits 4 through 0 of register 19h) to 0 through the serial management interface, although the content of the isolate register is not affected by the modification of phy address. in isolate mode, the LU3X32FT does not respond to packet data present at txd[3:0], txen, and txer inputs and presents a high impedance on the txclk, rxclk, rxdv, rxer, rxd[3:0], col, and crs outputs. the LU3X32FT will continue to respond to all management transactions. serial management interface each port of the LU3X32FT supports smi. the serial management interface (smi) is used to both obtain status from and to configure each phy. this mechanism corresponds to the mii spec for 100base-x (clause 22) and sup- ports registers 0 through 6. additional vendor-specific registers are implemented within the range of 16 to 31. all the registers are described in the register section.
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 14 lucent technologies inc. functional description (continued) management register access . the smi consists of two pins, management data clock (mdc) and management data input/output (mdio). the LU3X32FT is designed to support an mdc frequency ranging up to the ieee speci- fication of 2.5 mhz. each mdio line is bidirectional and may be shared by up to 32 devices (16 LU3X32FT devices). the mdio pin requires a pull-up resistor which, during idle and turnaround periods, will pull mdio to a logic one state. each mii management data frame is 64 bits long. the first 32 bits are preamble consisting of 32 contiguous logic one bits on mdio and 32 corresponding cycles on mdc. following preamble is the start-of-frame field indi- cated by a <01> pattern. the next field signals the operation code (op): <10> indicates read from mii manage- ment register operation, and <01> indicates write to mii management register operation. the next two fields are phy device address and mii management register address. both of them are 5-bits wide, and the most-significant bit is transferred first. during read operation, a 2-bit turnaround (ta) time spacing between register address field and data field is pro- vided for the mdio to avoid contention. following the turnaround time, a 16-bit data stream is read from or written into the mii management registers of the LU3X32FT. the LU3X32FT supports a preamble suppression mode as indicated by a 1 in bit 6 of the basic mode status regis- ter (bmsr, address 01h.) if the station management entity (i.e., mac or other management controller) determines that all phys in the system support preamble suppression by reading a 1 in this bit, then the station management entity need not generate preamble for each management transaction. the LU3X32FT requires a single initialization sequence of 32 bits of preamble following powerup/hardware reset. this requirement is generally met by the man- datory pull-up resistor on mdio or the management access made to determine whether preamble suppression is supported. while the LU3X32FT will respond to management accesses without preamble, a minimum of one idle bit between management transactions is required as specified in ieee 802.3u. the phy device addresses for the LU3X32FT are stored in the phy address registers (register address 19h). it is initialized by the four i/o pins designated as phy[4:1] during powerup or hardware reset. phy[0] is forced to 0 for port 0 and 1 for port 1. the entire phy address can be changed by writing into phy address register, address 19h. mdio interrupt . the LU3X32FT implements interrupt capability that can be used to notify the management station of certain events. it generates an active-low interrupt pulse on the mdioint output pin whenever one of the inter- rupt status registers (register address 1eh) becomes set while its corresponding interrupt mask register (register address 1dh) is unmasked. reading the interrupt status register (register 1eh) shows the source of the interrupts, and clears all bits of the interrupt status register. in addition to the mdioint pins, the LU3X32FT can also support the interrupt scheme used by the ti thunderlan * mac. this option can be enabled by setting bit 11 of register 17h. whenever this bit is set, the interrupt is signaled through both the mdioint pin and embedded in the mdio signal. * ti is a registered trademark and thunderlan is a trademark of texas instruments, inc.
lucent technologies inc. 15 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx functional description (continued) 100base-x module the LU3X32FT implements a 100base-x compliant pcs and pma and 100base-tx compliant tp-pmd for each port as illustrated in figure 3. bypass options for each of the major functional blocks within the 100base-x pcs provide flexibility for various applications. 100 mbits/s phy loopback is included for diagnostic purposes. 5-7909(f).r2 figure 3. 100base-x data path (per port) 100base-x transmitter the 100base-x transmitter consists of functional blocks which convert synchronous 4-bit nibble data, as provided by the mii, to a 125 mbits/s serial data stream. this data stream may be routed either to the on-chip twisted-pair pmd for 100base-tx signaling, or to an external fiber-optic pmd for 100base-fx applications. the LU3X32FT implements the 100base-x transmit state machines as specified in the ieee 802.3u standard, clause 24 and comprises the following functional blocks in its data path: n symbol encoder n scrambler block n parallel/serial converter and nrz/ nrzi encoder block fotx rxen rxdv crs rxclk descrambler serial-to- clock recovery equalizer 5b/4b byp_4b5b byp_align receive rxd[3:0] forx fosd tprx 100base-x receiver txd[3:0] col txclk txen txer parallel-to-serial scrambler byp_scr byp_align mlt-3 state 10/100 pecl driver tptx 100base-x transmitter decode 100m phy state byp_ scr transmit state 4b/5b encode byp_4b5b transmit loopback path parallel machine
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 16 lucent technologies inc. functional description (continued) symbol encoder . the symbol encoder converts 4-bit (4b) nibble data generated by the mac into 5-bit (5b) sym- bols for transmission. this conversion is required to allow control symbols to be combined with data symbols. refer to the table below for 4b to 5b symbol mapping. following onset of the txen signal, the 4b/5b symbol encoder replaces the first two nibbles of the preamble from the mac frame with a /j/k code-group pair (11000 10001) start-of-stream delimiter (ssd). the symbol encoder then replaces subsequent 4b codes with corresponding 5b symbols. following negation of the txen signal, the encoder substitutes the first two idle symbol with a /t/r code-group pair (01101 00111) end-of-stream delimiter (esd) and then continuously injects idle symbols into the transmit data stream until the next transmit packet is detected. assertion of the txer input while the txen input is also asserted will cause the LU3X32FT to substitute halt code-groups for the 5b code derived from data present at txd[3:0]. however, the ssd (/j/k) and esd (/t/r) will not be substituted with halt code-groups. as a result, the assertion of txer while txen is asserted will result in a frame properly encapsulated with the /j/k and /t/r delimiters which contains halt code-groups in place of the data code-groups. the 100 mbits/s symbol decoder translates all invalid code groups into 0eh by default. in case the accept halt register is set (bit 5 of register 18h), the halt code group (00100) is translated into 05h instead.
lucent technologies inc. 17 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx functional description (continued) table 12. symbol code scrambler s y mbol name 5b code [4:0] 4b code [3:0] inter p retation 0 11110 0000 data 0 1 01001 0001 data 1 2 10100 0010 data 2 3 10101 0011 data 3 4 01010 0100 data 4 5 01011 0101 data 5 6 01110 0110 data 6 7 01111 0111 data 7 8 10010 1000 data 8 9 10011 1001 data 9 a 10110 1010 data a b 10111 1011 data b c 11010 1100 data c d 11011 1101 data d e 11100 1110 data e f 11101 1111 data f i 11111 undefined idle: interstream fill code j 11000 0101 first start-of-stream delimiter k 10001 0101 second start-of-stream delimiter t 01101 undefined first end-of-stream delimiter r 00111 undefined second end-of-stream delimiter h 00100 undefined halt: transfer error v 00000 undefined invalid code v 00001 undefined invalid code v 00010 undefined invalid code v 00011 undefined invalid code v 00101 undefined invalid code v 00110 undefined invalid code v 01000 undefined invalid code v 01100 undefined invalid code v 10000 undefined invalid code v 11001 undefined invalid code
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 18 lucent technologies inc. functional description (continued) scrambler block . for 100base-tx applications, the scrambler is required to control the radiated emissions at the media connector and on the twisted-pair cable. the LU3X32FT implements a data scrambler as defined by the tp-pmd stream cipher function per port. the scrambler uses an 11-bit ciphering linear feedback shift register (lfsr) with the following recursive linear function: x[n] = x[n C 11] + x[n C 9] (modulo 2) the output of the lfsr is combined with data from the encoder via an exclusive-or logic function. by scrambling the data, the total energy launched onto the cable is randomly distributed over a wide frequency range. a seed value for the scrambler function can be loaded by setting bit 4 of register 18h. when this bit is set, the con- tent of bits 10 through 0 of register 19h, that compose of the 5-bit phy address and a 6-bit user seed, will be loaded into the lfsr. by specifying unique seed value for each phy in a system, the total emi energy produced by a repeater application can be reduced. parallel to serial & nrz-nrzi conversion . after the transmit data stream is scrambled, data is loaded into a shift register and clocked out with a 125 mhz clock into a serial bit stream. the serialized data is further converted from nrz to nrzi format, which produces a transition on every logic 1 and no transition on logic 0. collision detect . during 100 mbits/s half-duplex operation, collision condition is detected if the transmitter and receiver become active simultaneously. collision detection is indicated by the col pin of the mii. for full-duplex applications, the col signal is never asserted. a collision test register exists at address 0 bit 7. 100base-x receiver the 100base-x receivers consist of functional blocks required to recover and condition the 125 mbits/s receive data stream. the LU3X32FT implements the 100base-x receive state machine diagram as given in ansi/ ieee standard 802.3u, clause 24 for each port. the 125 mbits/s receive data stream may originate from the on-chip twisted-pair transceiver in a 100base-tx application. alternatively, the receive data stream may be generated by an external optical receiver as in a 100base-fx application. each receiver block consists of the following functional blocks: n clock recovery module n nrzi/ nrz and serial/parallel decoder n descrambler n symbol alignment block n symbol decoder n collision detect block n carrier sense block n stream decoder block clock recovery . the clock recovery module accepts 125 mbits/s scrambled nrzi data stream from either the on- chip 100base-tx receiver or from an external 100base-fx transceiver. the LU3X32FT uses an onboard digital phase-locked loop (pll) to extract clock information of the incoming nrzi data, which is then used to retime the data stream and set data boundaries. after power-on or reset, the pll locks to a free-running 25 mhz clock derived from the external clock source. when initial lock is achieved, the pll switches to lock to the data stream, extracts a 125 mhz clock from the data, and uses it for bit framing of the recovered data.
lucent technologies inc. 19 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx functional description (continued) nrzi/nrz & serial/parallel conversion . the recovered data is converted from nrzi to nrz format. the data is not necessarily aligned to 4b/5b code-groups boundary. data descrambling . the descrambler acquires synchronization with the data stream by recognizing idle bursts of 40 or more bits and locking its deciphering linear feedback shift register (lfsr) to the state of the scrambling lfsr. upon achieving synchronization, the incoming data is xored by the deciphering lfsr and descrambled. in order to maintain synchronization, the descrambler continuously monitors the validity of the unscrambled data that it generates. to ensure this, a link state monitor and a hold timer are used to constantly monitor the synchroni- zation status. upon synchronization of the descrambler, the hold timer starts a 722 m s countdown. upon detection of sufficient idle symbols within the 722 m s period, the hold timer will reset and begin a new countdown. this mon- itoring operation will continue indefinitely given a properly operating network connection with good signal integrity. if the link state monitor does not recognize sufficient unscrambled idle symbols within the 722 m s period, the descrambler will be forced out of the current state of synchronization and reset in order to reacquire synchroniza- tion. register 18h, bit 3, can be used to extend the timer to 2 ms. symbol alignment . the symbol alignment circuit in the LU3X32FT determines code word alignment by recogniz- ing the /j/k delimiter pair. this circuit operates on unaligned data from the descrambler. once the /j/k symbol pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. symbol decoding . the symbol decoder functions as a look up table that translates incoming 5b symbols into 4b nibbles. the symbol decoder first detects the /j/k symbol pair preceded by idle symbols and replaces the symbol with mac preamble. all subsequent 5b symbols are converted to the corresponding 4b nibbles for the duration of the entire packet. this conversion ceases upon the detection of the /t/r symbol pair denoting the end of stream delimiter (esd). the translated data is presented on the rxd[3:0] signal lines with rxd[0] represents the least- significant-bit of the translated nibble. valid data signal . the receive data valid signal (rxdv) indicates that recovered and decoded nibbles are being presented on the rxd[3:0] outputs synchronous to rxclk. rxdv is asserted when the first nibble of translated / j/k is ready for transfer over the media independent interface (mii). it remains active until either the /t/r delimiter is recognized, link test indicates failure, or no signal is detected. on any of these conditions, rxdv is deasserted. receiver errors . the rxer signals are used to communicate receiver error conditions. while the receiver is in a state of holding rxdv asserted, the rxer will be asserted for each code word that does not map to a valid code- group. 100base-x link monitor the 100base-x link monitor function allows the receivers to ensure that reliable data is being received. without reliable data reception, the link monitor will halt both transmit and receive operations until such time that a valid link is detected. the LU3X32FT performs the link integrity test as outlined in ieee 100base-x (clause 24) link monitor state dia- gram. the link status is multiplexed with 10 mbits/s link status to form the reportable link status bit in serial man- agement register 1, and driven to the ledlnk pin. when persistent signal energy is detected on the network, the logic moves into a link-ready state after approxi- mately 500 m s and waits for an enable from the autonegotiation module. when received, the link-up state is entered, and the transmit and receive logic blocks become active. should autonegotiation be disabled, the link integrity logic moves immediately to the link-up state after entering the link-ready state.
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 20 lucent technologies inc. functional description (continued) carrier sense . carrier sense (crs) for 100 mbits/s operation is asserted upon the detection of two non-contigu- ous zeros occurring within any 10-bit boundary of the receive data stream. the carrier sense function is independent of symbol alignment. for 100 mbits/s half-duplex operation, crs is asserted during either packet transmission or reception. for 100 mbits/s full-duplex operation, crs is asserted only during packet reception. when the idle symbol pair is detected in the receive data stream, crs is deasserted. in repeater mode, crs is only asserted due to receive activity. bad ssd detection . a bad start of stream delimiter (bad ssd) is an error condition that occurs in the 100base-x receiver if carrier is detected (crs asserted), and a valid /j/k set of code groups (ssd) is not received. if this condition is detected, then the LU3X32FT will assert rxer and present rxd[3:0] = 1110 to the mii for the cycles that correspond to received 5b code-groups until at least two idle code groups are detected. in addition, the false carrier counter (address 13h) will be incremented by one. once at least two idle code groups are detected, rxer and crs become de-asserted. far-end fault indication . autonegotiation provides a mechanism for transferring information from the local station to the link partner that a remote fault has occurred for 100base-tx. as autonegotiation is not currently specified for operation over fiber, the far-end fault indication function (fefi) provides this capability for 100base-fx applications. a remote fault is an error in the link that one station can detect while the other cannot. an example of this is a dis- connected wire at a stations transmitter. this station will be receiving valid data and will detect that the link is good via the link integrity monitor, but will not be able to detect that its transmission is not propagating to the other sta- tion. a 100base-fx station that detects such a remote fault may modify its transmitted idle stream from all ones to a group of 84 ones followed by a single 0. this is referred to as the fefi idle pattern. the fefi function is controlled by bit 11 of register 18h. it is initialized to 1 (enabled) if both the fosel pin and fefi_en pin are at logic high level during powerup or reset. if the fefi function is enabled, the LU3X32FT will halt all current operations and transmit the fefi idle pattern when fosd+/fosdC signal is deasserted following a good link indication from the link integrity monitor. transmission of the fefi idle pattern will continue until fosd+/ fosdC signal is asserted. if three or more fefi idle patterns are detected by the LU3X32FT, then bit 4 of the basic mode status register (address 01h) is set to one until read by management. additionally, upon detection of far-end fault, all receive and transmit mii activity is disabled/ignored. carrier integrity monitor . the carrier integrity monitor (cim) function protects the repeater from transient condi- tions that would otherwise cause spurious transmission due to a faulty link. this function is required for repeater applications and is not specified for node applications. the cim function is controlled by bit 10 of register 18h. it is initialized to 1 (enabled) if both the ndrptr pin and cimen pin are at logic high level during powerup or reset. if the cim determines that the link is unstable, the LU3X32FT will not propagate the received data or control signaling to the mii and will ignore data transmitted via the mii. the LU3X32FT will continue to monitor the receive stream for valid carrier events. the false carrier counter (address 13h) increments each time the link is unstable (bad ssd), the fcrs pin stays high as long as error con- dition exists. two back-to-back false carrier events will isolate the phy, incrementing the associated isolate counter (register address 12h) once.
lucent technologies inc. 21 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx functional description (continued) 100base-tx transceiver LU3X32FT implements tp-pmd compliant transceivers for 100base-tx operation. the differential transmit driver is shared by the 10base-t and 100base-tx subsystems. this arrangement results in one device that uses the same external magnetics for both the 10base-t and the 100base-tx transmission with simple rc component connections. the individually wave-shaped 10base-t and 100base-tx transmit signals are multiplexed in the transmit output driver section. transmit drivers . the LU3X32FT 100base-tx transmit drivers implement mlt-3 translation and wave-shaping functions. the rise/fall time of the output signal is closely controlled to conform to the target range specified in the ansi tp-pmd standard. twisted-pair receiver . for 100base-tx operation, the incoming signal is detected by the on-chip twisted-pair receivers that comprise the differential line receiver, an adaptive equalizer, and baseline wander compensation cir- cuits. the LU3X32FT uses adaptive equalizers which change filter frequency response in accordance with cable length. the cable length is estimated based on the incoming signal strength. the equalizer tunes itself automatically for any cable length to compensate for the amplitude and phase distortions incurred from the cable. 10base-t module the 10base-t transceiver modules are ieee 802.3 compliant. they include the receiver, transmitter, collision, heartbeat, loopback, jabber, waveshaper, and link integrity functions, as defined in the standard. figure 4 provides an overview for the 10base-t modules. the LU3X32FT 10base-t modules are comprised of the following functional blocks: n manchester encoder and decoder n collision detector n link test function n transmit driver and receiver n serial and parallel interface n jabber and sqe test functions n polarity detection and correction 5-7910(f) figure 4. 10base-t module data path (per port) tprx receive filter smart clock recovery 10base-t receive pcs rxclk crs rxdv rxd[3:0] col 10/100 transmit wave shaper 10base-t transmit pcs txen txer txd[3:0] txclk tptx filter squelch 10m phy loopback path driver
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 22 lucent technologies inc. functional description (continued) operation modes the LU3X32FT 10base-t modules are capable of operating in either half-duplex mode or full-duplex mode. in half- duplex mode, the LU3X32FT functions as an ieee 802.3 compliant transceiver with fully integrated filtering. the col pin signals squelch jabber, and the crs is asserted during transmit and receive. in full-duplex mode, the LU3X32FT can simultaneously transmit and receive data. manchester encoder/decoder . data encoding and transmission begins when the transmit enable input (txen) goes high and continues as long as the transceiver is in good link state. transmission ends when the transmit enable input goes low. the last transition occurs at the center of the bit cell if the last bit is a 1, or at the boundary of the bit cell if the last bit is 0. decoding is accomplished by a differential input receiver circuit and a phase-locked loop that separates the manchester-encoded data stream into clock signals and nrz data. the decoder detects the end of a frame when no more mid-bit transitions are detected. within one and a half bit times after the last bit, carrier sense is de- asserted. transmit driver and receiver . LU3X32FT integrates all the required signal conditioning functions in its 10base-t blocks such that external filters are not required. only an isolation transformer and impedance matching resistors are needed for the 10base-t transmit and receive interface. the internal transmit filtering ensures that all the har- monics in the transmit signal are attenuated properly. smart squelch . the smart squelch circuit is responsible for determining when valid data is present on the differen- tial receive. the LU3X32FT implements an intelligent receive squelch on the tprx differential inputs to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. the squelch circuitry employs a combination of amplitude and timing measurements (as specified in the ieee 802.3 10base-t standard) to deter- mine the validity of data on the twisted-pair inputs. the signal at the start of the packet is checked by the analog squelch circuit, and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. finally, the signal must exceed the original squelch level within a further 150 ns to ensure that the input waveform will not be rejected. only after all of these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present. valid data is considered to be present until the squelch level has not been generated for a time longer than 200 ns, indicating end-of-packet. once good data has been detected, the squelch levels are reduced to minimize the effect of noise causing premature end-of-packet detection. the receive squelch threshold level can be lowered for use in longer cable applications. this is achieved by setting bit 11 or register address 1ah. carrier sense . carrier sense (crs) may be asserted due to receive activity once valid data is detected via the smart squelch function. for 10 mbits/s half-duplex operation, crs is asserted during either packet transmission or reception. for 10 mbits/s full-duplex operation, the crs is asserted only due to receive activity. in repeater mode, crs is only asserted due to receive activity. crs is deasserted following an end of packet. collision detection . for half-duplex operation, a 10base-t collision is detected when the receive and transmit channels are active simultaneously. collisions are reported by the col signal on the mii. if the endec is transmit- ting when a collision is detected. the col signal remains set for the duration of the collision.
lucent technologies inc. 23 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx functional description (continued) sqe test function . approximately 1 m s after the transmission of each packet, a signal quality error (sqe) signal of approximately 10 bit times is generated (internally) to indicate successful transmission. sqe is reported as a pulse on the col signal of the mii. this function can be enabled by setting bit 12 of register 1ah. the sqe test function is disabled in full-duplex mode. jabber function . the jabber function monitors the LU3X32FTs output and disables the transmitter if it attempts to transmit a longer than legal-sized packet. if txen is high for greater than 24 ms, the 10base-t transmitter will be disabled and col will go active-high. once disabled by the jabber function, the transmitter stays disabled for the entire time that the txen signal is asserted. this signal has to be deasserted for approximately 256 ms (the unjab time) before the jabber function reenables the transmit outputs and de-asserts col signal. the jabber function can be disabled by setting bit 10 of register 1ah. link test function . a link pulse is used to check the integrity of the connection with the remote end. if valid link pulses are not received, the link detector disables the 10base-t twisted-pair transmitter, receiver, and collision detection functions. the link pulse generator produces pulses as defined in the ieee 802.3 10base-t standard. each link pulse is nominally 100 ns in duration and is transmitted every 16 ms, in the absence of transmit data. automatic link polarity detection . the LU3X32FT's 10base-t transceiver modules incorporate an automatic link polarity detection circuit. the inverted polarity is determined when seven consecutive link pulses of inverted polarity or three consecutive receive packets are received with inverted end-of-packet pulses. if the input polarity is reversed, the error condition will be automatically corrected and reported in bit 15 of register 1ch. the automatic link polarity detection function can be disabled by setting bit 3 of register 1ah. clock synthesizer the LU3X32FT implements a clock synthesizer that generates all the reference clocks needed from a single exter- nal frequency source. the clock source must be a ttl level signal at 25 mhz 50 ppm, as shown in figure 15.
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 24 lucent technologies inc. functional description (continued) autonegotiation the autonegotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest-performance mode of operation supported by both devices. fast link pulse (flp) bursts provide the signaling used to communicate autonegotiation abilities between two devices at each end of a link segment. for further detail regarding autonegotiation, refer to clause 28 of the ieee 802.3u specification. the LU3X32FT supports four different ethernet protocols, so the inclusion of autonegotiation ensures that the highest-performance protocol will be selected based on the ability of the link partner. the autonegotiation function within the LU3X32FT can be controlled either by internal register access or by the use of configuration pins. at powerup and at device reset, the configuration pins are sampled. if disabled, autonegotia- tion will not occur until software enables bit 12 in register 0. if autonegotiation is enabled, the negotiation process will commence immediately. when autonegotiation is enabled, the LU3X32FT transmits the abilities programmed into the autonegotiation advertisement register at address 04h via flp bursts. any combination of 10 mbits/s, 100 mbits/s, half-duplex, and full-duplex modes may be selected. autonegotiation controls the exchange of configuration infor- mation. upon successful autonegotiation, the abilities reported by the link partner are stored in the autonegotiation link partner ability register at address 05h. the contents of the autonegotiation link partner ability register are used to automatically configure to the highest- performance protocol between the local and far-end nodes. software can determine which mode has been config- ured by autonegotiation by comparing the contents of register 04h and 05h and then selecting the technology whose bit is set in both registers of highest priority relative to the following list: 1. 100base-tx full duplex (highest priority) 2. 100base-tx half duplex 3. 10base-t full duplex 4. 10base-t half duplex (lowest priority) the basic mode control register at address 00h provides control of enabling, disabling, and restarting of the auto- negotiation function. when autonegotiation is disabled the speed selection bit (bit 13) controls switching between 10 mbits/s or 100 mbits/s operation, while the duplex mode bit (bit 8) controls switching between full-duplex opera- tion and half-duplex operation. the speed selection and duplex mode bits have no effect on the mode of operation when the autonegotiation enable bit (bit 12) is set. the basic mode status register at address 01h indicates the set of available abilities for technology types (bits 15 to 10), autonegotiation ability (bit 3), and extended register capability (bit 0). these bits are hardwired to indicate the full functionality of the LU3X32FT. the bmsr also provides status on: n whether autonegotiation is complete (bit 5). n whether the link partner is advertising that a remote fault has occurred (bit 4). n whether a valid link has been established (bit 2). the autonegotiation advertisement register at address 04h indicates the autonegotiation abilities to be advertised by the LU3X32FT. all available abilities are transmitted by default, but any ability can be suppressed by writing to this register or configuring external pins. the autonegotiation link partner ability register at address 05h indicates the abilities of the link partner as indicated by autonegotiation communication. the contents of this register are considered valid when the autonegotiation complete bit (bit 5, register address 01h) is set.
lucent technologies inc. 25 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx functional description (continued) reset operation the LU3X32FT can reset each port either by hardware or software. a hardware reset is accomplished by applying a negative pulse, with a duration of at least 1 ms, to the rstz pin of the LU3X32FT during normal operation. a software reset is activated by setting the reset bit in the basic mode control register (bit 15, register 00h). this bit is self-clearing and, when set, will return a value of 1 until the software reset operation has completed. both hardware and software reset operations initialize all registers to their default values. this process includes re- evaluation of all hardware configurable registers. logic levels on several i/o pins are detected during the hardware and software reset period to determine the initial functionality of each of the ports. some of these pins are used as output ports after reset operation. care must be taken to ensure that the configuration setup will not interfere with normal operation. dedicated con- figuration pins can be tied to v cc or ground directly. configuration pins multiplexed with logic level output functions should be either weakly pulled-up or weakly pulled-down through resistors. configuration pins multiplexed with led outputs should be set up with one of the following circuits shown in figure 5. note that the 10 k w resistor is needed only for nondefault configuration. 5-7911(f) figure 5. hardware reset configurations phy address during hardware reset, the logic level of the phy address pins are latched into bits 4 through 1 of the phy address register, address 19h, respectively. because the LU3X32FT implements two physical layers, the phy address bit 0 is internally set to 0 for port 0 and 1 for port 1. this 5-bit address is used as the phy address for serial manage- ment interface communication. note that initializing all configurable phy addresses to zero automatically isolates the mii interface of port 0. node/repeater mode select a logic 1 level on pins 57 or 110 during reset configures the port to function as a repeater. otherwise, this device will function in node mode. fiber mode select a logic 1 level on pins 51 or 116 during reset configures the 100 mbits/s section of the respective port for 100base- fx operation. i/o pin i/o pin logic 1 configuration logic 0 configuration 10 k w 10 k w v cc
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 26 lucent technologies inc. functional description (continued) autonegotiation & speed configuration the three pins listed in table 13 configure the speed capability of LU3X32FT. the logic state of these pins, at pow- erup or reset, are latched into the advertisement register (register address 04h) for autonegotiation purpose. these pins are also used for evaluating the default value in the base mode control register (register 00h) according to the table 13. table 13. initial value of autonegotiation registers configuration pins at reset registers initial value autonen pins 45, 122 100fden pins 42, 125 (reg 4.8) 10fden pins 82, 85 (reg 4.6) autoneg reg 0.12 speed reg 0.13 duplex reg 0.8 01x011 001011 000010 1xx100
lucent technologies inc. 27 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx functional description (continued) 100base-x pcs configuration the logic state of bpscr and bpalign pins latched into bits 15 and 12 of the config 100 register at address 18h during powerup or reset. bit 14 of register 18h (bp4b5b) is initialized to 0 during power-on or reset. these regis- ters configure the functionality of 100base-x pcs (physical coding sublayer). register descriptions table 14. mii management registers legends le g end for tables 15 32 : roread onl y r/wread and write capable scself-clearin g lllatchin g low, unlatch on read lhlatchin g hi g h, unlatch on read cor clear on read register address register name basic/extended 0h control register b 1h status register b 2h3h phy identifier register e 4h autonegotiation advertisement register e 5h autonegotiation link partner ability register e 6h autonegotiation expansion register e 7hfh ieee reserved e 12h isolate counter e 13h false carrier counter e 15h receive error counter e 17h phy control/status register e 18h config 100 register e 19h phy address register e 1ah config 10 register e 1bh status 100 register e 1ch status 10 register e 1dh interrupt mask register e 1eh interrupt status register e
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 28 lucent technologies inc. register description (continued) table 15. control register (per port) [register 0h] bit(s) name description r/w default 15 reset 1phy reset. 0normal operation. settin g this bit initiates the software reset function that resets the entire LU3X32FT device, except for the phase-locked loop circuit. it will relatch in all hardware confi g - uration pin values and set all re g isters to their default values. the software reset process takes 25 m s to complete. this bit, which is self-clearin g , returns a value of 1 until the reset process is complete. r/w sc 0h 14 loopback 1enable loopback mode. 0disable loopback mode. this bit controls the phy loopback opera- tion that isolates the network transmitter outputs (tptx and fotx) and routes the mii transmit data to the mii receive data path. this function should only be used when autonegotiation is disabled (bit 12 = 0). the specific phy (10base-t or 100base-x) used for this operation is determined by bits 12 and 13 of this regis- ter. r/w 0h 13 speed selection 1100 mbits/s. 010 mbits/s. link speed is selected b y this bit or b y autone g otiation if bit 12 of this re g ister is set ( in which case, the value of this bit is i g nored ) . at powerup or reset, this bit will be set unless autonen, 100fden, and 100hden pin are all in logic low state. r/w pin 12 autone g otiation enable 1enable autone g otiation process. 0disable autone g otiation process. this bit determines whether the link speed should be set up b y the autone g otiation process. it is set at powerup or reset if the autonen pin detects a lo g ic 1 input level. r/w pin 11 powerdown 1powerdown. 0normal operation. settin g this bit puts the LU3X32FT into powerdown mode. durin g the powerdown mode, tx and all led outputs are tri- stated, fotx output are turned off, and the mii interface is isolated. rstz is used to clear re g ister. r/w 0h
lucent technologies inc. 29 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx register description (continued) table 15 . control register (per port) [register 0h] (continued) bit(s) name description r/w default 10 isolate 1isolate phy from mii. 0normal operation. setting this control bit isolates the part from the mii, with the exception of the serial management interface. when this bit is asserted, the LU3X32FT does not respond to txd[3:0], txen, and txer inputs, and it presents a high impedance on its txclk, rxclk, rxdv, rxer, rxd[3:0], col, and crs outputs. this bit is initialized to 0 unless the configuration pins for the phy address are set to 00000h during powerup or reset. r/w pins 9 restart autone g otiation 1restart autone g otiation process. 0normal operation. settin g this bit while autone g otiation is enabled forces a new autone g otiation pro- cess to start. this bit is self-clearin g and returns to 0 after the autone g otiation pro- cess has commenced. r/w, sc 0h 8 duplex mode 1full-duplex mode. 0half-duplex mode. if autonegotiation is disabled, this bit determines the duplex mode for the link. at powerup or reset, this bit is set to 0 if the ndrptr bit indicates repeater operation. otherwise, this bit is set to 1 if autonen pin detects a logic 0 and either 100fden or 10fden pin detects a logic 1. r/w pin 7 collision test (only applica- ble while in phy loopback mode) 1enable col signal test. 0disable col signal test. when set, this bit will cause the col sig- nal of mii interface to be asserted in response to the assertion of txen. r/w 0h 6:0 reserved not used. ro 0h
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 30 lucent technologies inc. register description (continued) table 16. status register bit definitions (per port) [register 1h] bit(s) name description r/w default 15 100base-t4 1capable of 100base-t4. 0not capable of 100base-t4. this bit is hardwired to 0, indicatin g that the LU3X32FT does not support 100base-t4. ro 0h 14 100base-x full duplex 1capable of 100base-x full-duplex mode. 0not capable of 100base-x full-duplex mode. this bit is hardwired to 0, indicatin g that the LU3X32FT does not support 100base-x full- duplex mode. ro 1h 13 100base-x half duplex 1capable of 100base-x half-duplex mode. 0not capable of 100base-x half-duplex mode. this bit is hardwired to 1, indicatin g that the LU3X32FT supports 100base-x half-duplex mode. ro 1h 12 10 mbits/s full duplex 1capable of 10 mbits/s full-duplex mode. 0not capable of 10 mbits/s full-duplex mode. this bit is hardwired to 0, indicatin g that the LU3X32FT does not support 10base-t full- duplex mode. ro 1h 11 10 mbits/s half duplex 1capable of 10 mbits/s half-duplex mode. 0not capable of 10 mbits/s half-duplex mode. this bit is hardwired to 1, indicatin g that the LU3X32FT supports 10base-t half-duplex mode. ro 1h 10 100base-t2 1capable of 100base-t2. 0not capable of 100base-t2. this bit is hardwired to 0, indicatin g that the LU3X32FT does not support 100base-t2. ro 0h 9:7 reserved i g nore when read. ro 0h 6 mf preamble suppression 1accepts mana g ement frames with preamble suppressed. 0will not accept mana g ement frames with pre- amble suppressed. this bit is hardwired to 1, indicatin g that the LU3X32FT accepts mana g ement frame without preamble. a minimum of 32 preamble bits are re q uired followin g power-on or hardware reset. one idle bit is re q uired between an y two man- a g ement transactions as per ieee 802.3u speci- fication. ro 1h 5 autone g otiation complete 1autone g otiation process completed. 0autone g otiation process not completed. if autone g otiation is enabled, this bit indicates whether the autone g otiation process has been completed. ro 0h
lucent technologies inc. 31 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx table 17. phy identifier (per port) [register 2h] table 18. phy identifier (per port) [register 3h] 4 remote fault 1remote fault detected. 0remote fault not detected. this bit is latched to 1 if the rf bit in the autone- g otiation link-partner abilit y re g ister ( bit 13, re g is- ter address 05h ) is set or the receive channel meets the far end fault indication function criteria. it is unlatched when this register is read. ro, lh 0h 3autone g otiation abilit y 1capable of autone g otiation. 0not capable of autone g otiation. this bit defaults to 1, indicatin g that LU3X32FT is capable of autone g otiation. ro 1h 2 link status 1link is up. 0link is down. this bit reflects the current state of the link-test- fail state machine. loss of a valid link causes a 0 latched into this bit. it remains 0 until this re g ister is read b y the serial mana g ement interface. ro, ll 0h 1 jabber detect 1jabber condition detected. 0jabber condition not detected. durin g 10base-t operation, this bit indicates the occurrence of a j abber condition. it is imple- mented with a latchin g function so that it becomes set until it is cleared b y a read. ro, lh 0h 0 extended capabilit y 1extended re g ister set. 0no extended re g ister set. this bit defaults to 1, indicatin g that the LU3X32FT implements extended re g isters. ro 1h bit(s) name description r/w default 15:0 phy-id[15:0] ieee address. ro 0043h bit(s) name description r/w default 15:10 phy-id[15:0] ieee address/model no./ rev. no. this number may change in future revisions. ro 7421h bit(s) name description r/w default register description (continued) table 16. status register bit definitions (per port) [register 1h] (continued)
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 32 lucent technologies inc. register description (continued) table 19. advertisement (per port) [register 4h] table 20. autonegotiation link partner ability (per port) [register 5h] bit(s) name description r/w default 15 next pa g e 1capable of next pa g e function. 0not capable of next pa g e function. this bit is defaults to 0, indicatin g that LU3X32FT is not next pa g e capable. ro 0h 14 reserved reserved. ro 0h 13 remote fault 1remote fault has been detected. 0no remote fault has been detected. this bit is written b y serial mana g ement interface for the purpose of communicat- in g the remote fault condition to the auto- ne g otiation link partner. r/w 0h 12:10 ieee reserved these 3 bits default to 0. ro 0h 9 technolo gy abilit y field for 100base-t4 this bit defaults to 0, indicatin g that the LU3X32FT does not support 100base- t4. ro 0h 8 technology ability field for 100fden advertised ability of 100 mbits/s full- duplex of this phy. at powerup or reset, the logic level of 100fden pin is latched into this bit. r/w pin 7 technology ability field for 100hden advertised ability of 100 mbits/s half- duplex of this phy. r/w 1h 6 technology ability field for 10fden advertised ability of 10 mbits/s full-duplex of this phy. at powerup or reset, the logic level of 10fden pin is latched into this bit. r/w pin 5 technology ability field for 10hden advertised ability of 10 mbits/s half- duplex of this phy. r/w pin 4:0 selector field these 5 bits are hardwired to 00001h, indicatin g that the LU3X32FT supports ieee 802.3 csma/cd. ro 01h bit(s) name description r/w default 15 next pa g e 1capable of next pa g e function. 0not capable of next pa g e function. ro 0h 14 acknowled g e 1link partner acknowled g es reception of the abilit y data word. 0not acknowled g ed. ro 0h 13 remote fault 1remote fault has been detected. 0no remote fault has been detected. ro 0h 12:5 technolo gy abilit y field supported technolo g ies. ro 0h 4:0 selector field encodin g definitions. ro 0h
lucent technologies inc. 33 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx register description (continued) table 21. autonegotiation expansion register (per port) [register 6h] table 22. isolate counter (per port) [register 12h] table 23. false carrier counter (per port) [register 13h] bit(s) name description r/w default 15:5 reserved reserved. ro 0h 4 parallel detection fault 1fault has been detected. 0no fault detected. this bit is set if the parallel detection fault state of the autone g otiation arbitration state machine is visited durin g the auto- ne g otiation process. it will remain set until this re g ister is read. ro, lh 0h 3 link partner next pa g e able 1link partner is next pa g e capable. 0link partner is not next pa g e capable. this bit indicates whether the link partner is next pa g e able. it is meanin g ful onl y when the autone g otiation complete bit ( bit 5, re g ister 1 ) is set. ro 0h 2next pa g e able 1local device is next pa g e capable. 0local device is not next pa g e capable. this bit defaults to 0 indicatin g that LU3X32FT is not next pa g e able. ro 0h 1pa g e received 1a new pa g e has been received. 0no new pa g e has been received. this bit is latched to 1 when a new link code word pa g e has been received. this bit is automaticall y cleared when the autone g otiation link partner abilit y re g is- ter ( re g ister 05h ) is read b y mana g ement interface. ro, lh 0h 0 link partner autone g otiation able 1link partner is autone g otiation able. 0link partner is not autone g otiation able. ro 0h bit(s) name description r/w default 15:8 reserved reserved. ro 0h 7:0 cim isolate counter number of times isolated since reset or read. may roll over depending on value of csmode bit (bit 13 of register 17h). ro, cor 0h bit(s) name description r/w default 15:0 false carrier count number of false carrier conditions since reset or read. the counter is incremented once for each packet that has false carrier condition detected. this counter may roll over depending on value of csmode bit (bit 13 of register 17h). ro, cor 0h
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 34 lucent technologies inc. register description (continued) table 24. receive error counter (per port) [register 15h] table 25. phy control/status register (per port) [register 17h] bit(s) name description r/w default 15:0 rx error count number of receive errors since last reset. the counter is incremented once for each packet that has receive error condition detected. this counter may roll over depending on value of the csmode bit (bit 13 of register 17h). ro, cor 0h bit(s) name description r/w default 15 ndrptr 1repeater mode. 0node mode. this bit determines whether LU3X32FT is operating as a node or a repeater. it is ini- tialized to the logic level of ndrptr pin at powerup or reset. ro pin 14 fosel 1fiber mode. 0tx mode. for 100base-x operation, this bit deter- mines whether LU3X32FT interfaces with the network through the internal 100base- tx transceiver or using external fiber-optic transceiver. it is initialized to the logic level of fosel pin at powerup or reset. ro pin 13 csmode 1counter sticks at ffffh. 0counters roll over. this bit controls the operation of isolate counter, false carrier counter, and receive error counters. r/w 0h 12 tptxtr 13-state transmit pairs. 0normal operation. when this bit is set, the twisted-pair trans- mitter outputs of all four ports are tri- stated. r/w pin 11 thunderlan interrupt enable 1mdio thunderlan interrupt enabled. 0mdio thunderlan interrupt disabled. this bit enables/disables the ti thunderlan interrupt mechanism. r/w 0h 10 mf preamble suppression enable 1mdio preamble suppression enabled. 0mdio preamble suppression disabled. LU3X32FT can accept mana g ement frames without preamble as described in bit 6 of re g ister 1h. this bit allows the user to enable or disable the preamble sup- pression function. r/w 1h 9 speed status 1part is in 100 mbits/s mode. 0part is in 10 mbits/s mode. this value is not defined durin g the auto- ne g otiation period. ro 0h
lucent technologies inc. 35 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx register description (continued) table 25. phy control/status register (per port) [register 17h] (continued) bit(s) name description r/w default 8 duplex status 1part is in full-duplex mode. 0part is in half-duplex mode. this value is not defined during the auto- negotiation period. ro 0h 7 activity led on 1ledtx/actled active on both trans- mit and receive. 0ledtx/actled active on transmit only. r/w 0h 6 ledrx off 13-state ledrx output. 0normal operation. r/w 0 5 ledtx/actled off 13-state ledtx/actled output. 0normal operation. r/w 0 4 ledlnk off 13-state ledlnk output. 0normal operation. r/w 0 3 ledcol off 13-state ledcol output. 0normal operation. r/w 0 2 ledfd off 13-state ledfd output. 0normal operation. r/w 0 1 ledsp off 13-state ledsp output. 0normal operation. r/w 0 0 led pulse stretching disable 1led pulse stretching disabled. 0led pulse stretching enabled. when set to 0, all led outputs are stretched 48 ms72 ms. r/w 0
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 36 lucent technologies inc. register description (continued) table 26. config 100 register (per port) [register 18h] bit(s) name description r/w default 15 bpscr 1disable scrambler/descrambler. 0enable scrambler/descrambler. this bit is initialized to the logic level of bpscr pin at powerup or reset. r/w pin 14 bp4b5b 1disable 4b/5b encoder/decoder. 0enable 4b/5b encoder/decoder. this bit is initialized to the logic level of bp4b5b pin at powerup or reset. r/w pin 13 reserved reserved. ro 0h 12 bpalign 1pass unaligned data to mii. 0pass aligned data to mii. this bit is initialized to the logic level of bpalign pin at powerup or reset. r/w pin 11 enable fefi 1enable fefi. 0disable fefi. this bit enables/disables far-end fault indicator function for 100base-fx and 10base-t opera- tion. it is initialized to 1 if the logic level of the fosel pin and the fefi_en/10hden/ledfd pin are both high at powerup or reset. after reset, this bit is writable if and only if the fosel register (bit 14 of register 17h) is set. r/w pin 10 enable cim 1enable cim. 0disable cim. this bit enables/disables carrier integrity moni- tor function for repeater operation. it is initialized to 1 only if both ndrptr and cimen pins indicates logic 1 during powerup or reset. r/w pin 9 force good link 100 1force g ood link in 100 mbits/s mode. 0normal operation. r/w 0h 8:6 reserved reserved. ro 00 5 accept halt 1passes halt s y mbols to the repeater core. 0normal operation. r/w 0h 4 load seed 1loads the scrambler seed. 0normal operation. settin g this bit loads the user seed stored in re g ister 19h into the 100base-x scrambler. the content of this bit returns to 0 after the loadin g process is completed and no transmit is active. r/w, sc 0h 3 burst mode 1burst mode. 0normal operation. settin g this bit expands the 722 m s scrambler time-out period to 2,000 m s. r/w 0h 2:0 reserved reserved. ro 0h
lucent technologies inc. 37 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx register description (continued) table 27. phy address register (per port) [register 19h] table 28. config 10 register (per port) [register 1ah] bit(s) name description r/w default 15:11 reserved reserved. ro 0h 10:5 user seed user-modifiable seed data. when the load seed bit (bit 4 of register 18h) is set, bits 10 through 0 of this register are loaded into the 100base-x scrambler. a description is given in the symbol encoder section. r/w 21h 4:1 phy address 4 throu g h 1 these 4 bits, together with phy address 0, store the part address used by the serial management interface. phy address of 00000 has the special function of isolating the part from the mii. these bits are initialized to the logic levels of phy[4:1] pins at powerup or reset. r/w pin 0 phy address 0 the least significant bit of phy address. after powerup or reset, this bit is initial- ized to 0 for port 0 and 1 for port 1. r/w 0/1 bit(s) name description r/w default 15 10 mbits/s serial mode 110 mbits/s serial mode. 010 mbits/s nibble mode. during 10base-t operation, this bit deter- mines whether the mii will be operating in nib- ble mode or serial mode. it is initialized to 0h at powerup and reset unless the logic level of fosel pin is 0 and ser10 pin is 1. ro pin 14 force 10 me g good link 1force 10 mbits/s g ood link. 0normal operation. r/w 0h 13 reserved reserved. r/w 1h 12 sqe_en 1si g nal q ualit y error test enabled. 0default sqe is disabled. r/w 0h 11 low s q uelch select 1low s q uelch level selected. 0normal s q uelch level selected. r/w 0h 10 jabber disable 1jabber function disabled. 0normal operation. r/w 0h 9:7 reserved reserved. ro 0h 6 powerdown mode 1powers down the phy core completel y . the part comes out of this mode after a reset is asserted and deasserted. 0normal operation. r/w 0h 5:4 reserved reserved. ro 0h 3 autopolarit y disable 1disable autopolarit y function. 0enable autopolarit y function. r/w 0h 2:0 reserved reserved. ro 0h
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 38 lucent technologies inc. register description (continued) table 29. status 100 register (per port) [register 1bh] table 30. status 10 register (per port) [register 1ch] table 31. interrupt mask register (per port) [register 1dh] bit(s) name description r/w default 15 isolate status 1phy is isolated ( cim ) . 0normal operation. ro, lh 0h 14 reserved reserved. ro 0h 13 pll lock status 1100 mbits/s pll locked. 0100 mbits/s pll not locked. ro 0h 12 false carrier status 1false carrier detected. 0normal operation. ro, lh 0h 11:0 reserved reserved. ro 0h bit(s) name description r/w default 15 polarity 1polarity of cable is swapped. 0polarity of cables is correct. ro 0h 14:0 reserved reserved ro 0h bit(s) name description r/w default 15 false carrier status 0enable interrupt. 1disable interrupt. r/w 0h 14 receiver error counter full 0enable interrupt. 1disable interrupt. r/w 0h 13 isolate error counter full 0enable interrupt. 1disable interrupt. r/w 0h 12 remote fault 0enable interrupt. 1disable interrupt. r/w 0h 11 autoneg. complete 0enable interrupt. 1disable interrupt. r/w 0h 10 link up 0enable interrupt. 1disable interrupt. r/w 0h 9 link down 0enable interrupt. 1disable interrupt. r/w 0h 8 data recovery 100 lock up 0enable interrupt. 1disable interrupt. r/w 0h 7 data recovery lock down 0enable interrupt. 1disable interrupt. r/w 0h 6 reserved reserved. ro 0h 5:0 reserved reserved. ro 0h
lucent technologies inc. 39 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx register description (continued) table 32. interrupt status register (per port) [register 1eh] bit(s) name description r/w default 15 false carrier counter full 1false carrier counter has rolled over. 0false carrier counter has not rolled over. ro, lh 0h 14 receiver error counter full 1receive error counter has rolled over. 0receive error counter has not rolled over. ro, lh 0h 13 isolate counter full 1isolate counter has rolled over. 0isolate counter has not rolled over. ro, lh 0h 12 remote fault 1remote fault observed by phy. 0remote fault not observed by phy. ro, lh 0h 11 autonegotiation complete 1autonegotiation has completed. 0autonegotiation has not completed. ro, lh 0h 10 link up 1link is up. 0no change on link status. ro, lh 0h 9 link down 1link has gone down. 0no change on link status. ro, lh 0h 8 data recovery 100 lock up 1data recovery has locked. 0data recovery is not locked. ro, lh 0h 7 data recovery 100 lock down 1data recovery is not locked. 0data recovery has locked. ro, lh 0h 6 reserved reserved. ro 0h 5:0 reserved reserved. ro 0h
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 40 lucent technologies inc. absolute maximum ratings (t a = 25 c) stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. table 33 . absolute maximum ratings table 34. operating conditions * power dissipations are specified at 3.3 v and 25 c. this is the power dissipated by each port of the LU3X32FT. parameter symbol min max unit ambient operating temperature t a 070 c storage temperature t stg C65 150 c maximum supply voltage 3.46 v voltage on mll input pins with respect to ground C0.5 5.25 v voltage on any other pin with respect to ground C0.5 3.46 v parameter symbol min typ max unit operating supply voltage 3.135 3.3 3.46 v power dissipation * : 100 mbits/s tx 100 mbits/s fx 10 mbits/s autonegotiating p d p d p d p d 140 120 150 30 ma ma ma ma
lucent technologies inc. 41 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx electrical characteristics table 35. dc characteristics parameter symbol conditions min max unit recommended power supply v dd v ss 3.0 0.0 3.8 0.0 v v supply current100base-tx (per port) i dd v dd = 3.3 v, v ss = 0.0 v full-duplex traffic 148 ma supply current10base-tx (per port) i dd v dd = 3.3 v, v ss = 0.0 v full-duplex traffic 156 ma supply currentautonegotiation mode (per port) i dd v dd = 3.3 v, v ss = 0.0 v no link 70ma supply current100base-fx (per port) i dd v dd = 3.3 v, v ss = 0.0 v full-duplex traffic 120 ma ttl input high voltage v ih v dd = 3.3 v, v ss = 0.0 v 2.0 v ttl input low voltage v il v dd = 3.3 v, v ss = 0.0 v 0.8 v ttl output high-voltage mll pins v oh v dd = 3.3 v, v ss = 0.0 v 2.4 v ttl output low-voltage mll pins v ol v dd = 3.3 v, v ss = 0.0 v 0.4 v ttl output high-voltage led pins v oh2 v dd = 3.3 v, v ss = 0.0 v i oh = 10ma 3.0 v ttl output low-voltage led pins v ol2 v dd = 3.3 v, v ss = 0.0 v i oh = 10ma 0.3v pecl input high voltage v ihpecl v dd C1.16 v dd C0.88 v pecl input low voltage v ilpecl v dd C1.81 v dd C1.47 v pecl output high voltage v ohpecl v dd C1.02 v pecl output low voltage v olpecl v dd C1.62 v oscillator input (25 mhz) x in C50 50 ppm input capacitance mll c in 8pf
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 42 lucent technologies inc. clock timing table 36. system clock [xin] note: specified at + 50 ppm. 5-7912(f).a figure 6. system clock [x in ] symbol description min max unit t1 clock high pulse width 17 23 ns t2 clock low pulse width 17 23 ns t3 clock period 40 40 ns x in t2 t1 t3
lucent technologies inc. 43 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx clock timing (continued) table 37. transmit clock (input and output) * specified at 100 ppm. 5-7913(f) figure 7. transmit clock (input and output) symbol description min max unit t1 txclk high pulse width (100 mbits/s) 14 26 ns txclk high pulse width (10 mbits/s nibble) 140 260 ns txclk high pulse width (10 mbits/s serial) 35 65 ns t2 xin rise to txclk rise (100 mbits/s) 14 ns xin rise to txclk rise (10 mbits/s nibble) 28 ns t3 txclk low pulse width (100 mbits/s) 14 26 ns txclk low pulse width (10 mbits/s nibble) 140 260 ns txclk low pulse width (10 mbits/s serial) 35 65 ns t4 txclk period (100 mbits/s) 40 40 ns txclk period (10 mbits/s nibble) 400 400 ns txclk period (10 mbits/s serial) 100 100 ns txclk t2 t1 t4 x in t3
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 44 lucent technologies inc. clock timing (continued) table 38. management clock 5-7914(f) figure 8. management clock symbol description min max unit t1 mdc high pulse width 200 ns t2 mdc low pulse width 200 ns t3 mdc period 400 ns t4 mdio(i) setup to mdc rising edge 10 ns t5 mdio(i) hold time from mdc rising edge 10 ns t6 mdio(o) valid from mdc rising edge 0 300 ns mdc mdio(i) mdio(o) t1 t2 t3 t4 t5 t6
lucent technologies inc. 45 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx clock timing (continued) table 39. mii receive timing * load = tbd. 5-7915(f).a figure 9. mii receive timing symbol description min max unit t1 rxer, rxdv, rxd[3:0] setup to rxclk rise 10 ns t2 rxer, rxdv, rxd[3:0] hold after rxclk rise 10 ns t3 rxclk high pulse width (100 mbits/s) 14 26 ns rxclk high pulse width (10 mbits/s mii) 140 260 ns rxclk high pulse width (10 mbits/s serial) 35 65 ns t4 rxclk low pulse width (100 mbits/s) 14 26 ns rxclk low pulse width (10 mbits/s mii) 140 260 ns rxclk low pulse width (10 mbits/s serial) 35 65 ns t5 rxclk period (100 mbits/s) 40 40 ns rxclk period (10 mbits/s mii) 400 400 ns rxclk period (10 mbits/s serial) 100 100 ns t6 miiena assertion to rx valid 10 50 ns t7 miiena deassertion to rx 3-state* 140 ns rxclk rxer, rxdv, t3 t5 t4 t1 rxd[3:0] t2 crs t6 t7
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 46 lucent technologies inc. clock timing (continued) table 40. mii transmit timing 5-7916(f) figure 10. mii transmit timing symbol description min max unit t1 txer, txen, txd[3:0] setup to txclk rise 10 ns t2 txer, txen, txd[3:0] delay after txclk rise 0 25 ns txclk txer, txen, t2 txd[3:0] t1 data data
lucent technologies inc. 47 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx clock timing (continued) table 41. transmit timing 5-7917(f) figure 11. transmit timing symbol description min max unit t1 txen sampled to crs high (100 mbits/s) 0 4 bits txen sampled to crs high (10 mbits/s) 1.5 bits t2 txen sampled to crs low (100 mbits/s) 0 16 bits txen sampled to crs low (10 mbits/s) 16 bits t3 transmit latency (100 mbits/s) 6 14 bits transmit latency (10 mbits/s) 4 bits t4 sampled txen inactive to end of frame (100 mbits/s) 17bits sampled txen inactive to end of frame (10 mbits/s) 5bits txclk crs t3 t1 t2 txen tptx preamble t4
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 48 lucent technologies inc. clock timing (continued) table 42. receive timing 5-7918(f) figure 12. receive timing symbol description min max unit t1 receive frame to sampled edge of rxdv (100 mbits/s) 15bits receive frame to sampled edge of rxdv (10 mbits/s) 22bits t2 receive frame to crs high (100 mbits/s) 13 bits receive frame to crs high (10 mbits/s) 5 bits t3 end of receive frame to sampled edge of rxdv (100 mbits/s) 12bits end receive frame to sampled edge of rxdv (10 mbits/s) 4bits t4 end of receive frame to crs low (100 mbits/s) 13 24 bits end of receive frame to crs low (10 mbits/s) 4.5 bits rxclk crs t3 t2 rxdv tprx t4 data t1
lucent technologies inc. 49 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx clock timing (continued) table 43. reset and configuration timing 5-7919(f) figure 13. reset and configuration timing symbol description min max unit t1 power on to reset high 0.5 ms t2 reset pulse width 0.5 ms t3 configuration pin setup 0.5 ms t4 configuration pin hold 0.5 ms v cc rstz config t3 t4 t2 t1
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 50 lucent technologies inc. clock timing (continued) table 44. pmd characteristics 5-7920(f) figure 14. pmd characteristics symbol description min max unit t1 tptx+/tptxC rise time 3.0 5.0 ns t2 tptx+/tptxC fall time 3.0 5.0 ns t3 tp skew 0 500 ps t4 fotx+/fotxC rise time 1.4 ns t5 fotx+/fotxC fall time 1.4 ns t6 fo skew 0 200 ps t3 t2 t1 t5 t4 t6 tptx+ tptxC fotx+ fotxC
lucent technologies inc. 51 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx clock timing (continued) 5-6793(f).b figure 15. connection diagrams (frequency references) xin 25 mh z osc 50 ppm 25 mh z oscillator reference xin repeater clock buffer rxclk clk25[11:0] 25 mh z osc 100btx repeater clock distribution phy txclk rxclk xin phy txclk rxclk xin phy txclk rxclk xin phy txclk rxclk
LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 52 lucent technologies inc. clock timing (continued) 5-7921(f).r2 figure 16. connection diagrams (10/100btx operation) digital v dd transmit v dd receive v dd csv cc 75 w 75 w 75 w fb fb 0.1 m f22 m f 1 w 4.7 m f 50 w 1000 pf 0.1 m f0.1 m f 75 w rj45 tx+ txC rx+ rxC nc nc nc nc chassis_gnd tptx+ tptxC tprx+ tprxC ref100 ref10 receive gnd transmit gnd digital gnd 0.1 m f0.1 m f0.1 m f v cc gnd v cc transmit receive magnetic lu3x32 (1 port) 50 w 54 w 54 w 0.1 m f gnd gnd 301 w 4.64 k w 0.1 m f
lucent technologies inc. 53 preliminary data sheet LU3X32FT two-port 3 v 10/100 july 2000 ethernet transceiver tx/fx outline diagram 128-pin tqfp dimensions are in millimeters. 5-4427(f).r1 detail a detail b 1.60 max 0.50 typ seating plane 0.08 1.40 0.05 0.05/0.15 1 38 65 102 103 128 pin #1 identifier zone 16.00 0.20 14.00 0.20 20.00 0.20 22.00 0.20 64 39 0.19/0.27 0.08 m 0.106/0.200 detail b 0.25 0.45/0.75 1.00 ref gage plane seating plane detail a
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 1999 lucent technologies inc. all rights reserved july 2000 ds00-357lan (replaces ds99-308lan-1) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 325 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries:germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) LU3X32FT two-port 3 v 10/100 preliminary data sheet ethernet transceiver tx/fx july 2000 ordering information device code comcode package temperature LU3X32FT 108696063 128-pin tqfp 0 c to 70 c

▲Up To Search▲

Price & Availability of LU3X32FT

	To Download LU3X32FT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .